1. Field of the Invention
The present invention relates to a combined AD/DA converting apparatus.
2. Description of the Related Art
An optical disc device carries out a servo process of focusing, tracking, etc., usually through digital processing (e.g., see Japanese Patent Application Laid-Open Publication No. 2002-25078). Carrying out a servo process through digital processing requires an A/D converter that converts an analog signal, such as an FE (Focusing Error) signal and a TE (Tracking Error) signal generated based on an output signal from a pickup, into a digital signal. The servo process through digital processing also requires a DA converter that converts a digital signal resulting from the servo process into an analog signal used for controlling an optical pickup, etc.
FIG. 4 is a diagram of a general configurative example of a servo processor having an AD converter and a DA converter. The servo processor 100 includes a selector 110, sample hold circuit 111, the AD converter 112, a servo process circuit 113, the D/A converter 114, a selector 115, and sample hold circuits 116_1 to 116—n. 
A plurality of analog signals (VIN1 to VINn), such as FE signals and TE signals, are input to the selector 110, which then outputs one analog signal corresponding to a selection signal ADSEL. The signal output from the selector 110 is input to the AD converter 112 via the sample hold circuit 111. The servo process circuit 113 outputs a digital signal for carrying out a focusing process, tracking process, etc., based on a digital signal output from the AD converter 112. The digital signal output from the servo process circuit 113 is converted by the DA converter 114 into an analog signal, which is input to the selector 115. The analog signal input to the selector 115 is output to any one of the sample hold circuits 116_1 to 116—n based on a selection signal DASEL. Then, the sample hold circuits 116_1 to 116—n output analog signals (VO1 to VOn), which are used for carrying out the focusing process, tracking process, etc.
A sequential comparison type AD converter is used as the AD converter 112 in many cases. FIG. 5 is a diagram of a general configurative example of the AD converter provided as a sequential comparison type AD converter. The AD converter 112 includes a comparator circuit 120, a sequential comparison register 121, and a DA converter 122. In the AD converter 112, the comparator circuit 120 makes a size comparison of an input analog signal VIN and an analog signal resulting from DA conversion by the DA converter 122 of a digital signal stored in the sequential comparison register 121. Through the size comparison, the value of the digital signal stored in the sequential comparison register 121 is defined bit by bit sequentially from the most significant bit. After the definition of the least significant bit is over, a digital signal VADO remains stored in the sequential comparison register 121, and this digital signal VADO is a signal resulting from AD conversion of the analog signal VIN.
The servo processor 100 carries out AD conversion of the plurality of analog signals (VIN1 to VINn), and also carries out DA conversion to obtain the plurality of analog signals (VO1 to VOn). The servo processor 100, therefore, executes an AD conversion process and a DA conversion process in parallel, as shown in a timing chart of FIG. 6. In the case shown in FIG. 6, the selection signal ADSEL for selecting an analog signal VIN1 is output in timing at which a counter CNT, which counts up according to a clock CLK, is “0”. In timing at which the counter CNT is “4”, a reset signal ADRES turns to H level, a digital signal in the sequential comparison register 121 is set to an initial value, and the sample hold circuit 111 starts sampling. In timing at which the counter CNT is “5”, the sample hold circuit 111 holds the value of the analog signal VIN1. Then, in timing at which counter CNT is “6”, a defining process on the digital signal stored in the sequential comparison register 121 starts to define the value of the digital signal from the most significant bit (MSB) to the least significant bit (LSB) in sequence. When the definition of the least significant bit (LSB) is over, the digital signal VADO resulting from AD conversion of the analog signal VIN1 is obtained.
In parallel with the above AD conversion, in timing at which the counter CNT is “0”, the servo process circuit 113 starts outputting a digital signal that is to be output as an analog signal VO1. In timing at which the counter CNT is “1”, the selection signal DASEL for outputting the analog signal VO1 is output, and a sample hold circuit 116_1 starts sampling. Then, the sample hold circuit 116_1 holds the analog signal VO1 in timing at which the counter CNT is “7”. As a result, the analog signal VO1 is obtained as a signal resulting from DA conversion of the digital signal output from the servo process circuit 113.
When a sequential comparison type converter is employed as the AD converter 112, the servo processor 100 needs two DA converters 114 and 122. This increases the size of a circuit composing the servo processor 100. A method to deal with this problem has been known. According to the method, a circuit size increase is suppressed by causing a DA converter incorporated in a sequential comparison type AD converter to serve also as a DA converter for DA conversion when both AD conversion and DA conversion have to be carried out (e.g., see Japanese Patent Application Laid-Open Publication No. 2003-224473).
As described above, the servo processor 100 carries out AD conversion of the plurality of analog signals (VIN1 to VINn), and also carries out DA conversion to obtain the plurality of analog signals (VO1 to VOn). Because of this, when the servo processor 100 carries out AD conversion and DA conversion using such a combined AD/DA converting apparatus as disclosed in Japanese Patent Application Laid-Open Publication No. 2003-224473, the servo processor 100 cannot carry out AD conversion and DA conversion in parallel. As a result, for example, the servo processor 100 carries out AD conversion and DA conversion alternately again and again, which increases a processing time necessary for AD conversion and DA conversion, leading to a lower processing speed in executing such a process as focusing and tracking.